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Logic Synthesis and Verification Algorithms - a book by Hachtel, Gary D.

Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms( )
Author: Hachtel, Gary D.
Somenzi, Fabio
ISBN:978-1-4757-7036-0
Publication Date:Mar 2013
Publisher:Springer
Book Format:Paperback
List Price:USD $89.95
Book Description:

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and...
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Book Details
Pages:564
Detailed Subjects: Computers / Cad-Cam
Technology & Engineering / Electronics / Circuits / Vlsi & Ulsi
Computers / Logic Design
Physical Dimensions (W X L X H):6.942 x 9.906 x 0.472 Inches
Book Weight:2.477 Pounds

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